The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on current generation transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure, etc. Another technique that device designers have employed to improve device performance is to induce a desired stress in the channel region of a device, i.e., induce a tensile stress in the channel region of an NMOS device (to improve the mobility of charge-carrying electrons) and induce a compressive stress in the channel region of a PMOS device (to improve the mobility of charge-carrying holes). Various stress-memorization techniques are known to those skilled in the art.
One typical prior art process flow that is performed to form NMOS transistors with the desired tensile stress in a CMOS application is as follows. After the gate structures are formed, N-type extension and halo implants are formed for the N-type devices with the P-type devices masked, followed by extension and halo implants on the P-type devices with the N-type devices masked, a spacer is formed on the P-type devices, a cavity is etched in the source/drain regions of the P-type devices and an epi semiconductor material is formed in the cavities on the P-type devices. Next, a so-called SMT (Stress Memorization Technique) processing module is performed on the N-type device. A spacer is formed on the N-type devices and an amorphization implant process is performed using a material such as germanium to amorphize the source/drain region (e.g., using germanium at about 55 keV, 3e14 ion/cm2 dose). Thereafter, the SMT module involves forming a layer of silicon dioxide (e.g., about 4 nm thick) on the substrate, forming a capping material layer, e.g., a thick layer of silicon nitride (e.g., about 40 nm thick) with the desired intrinsic stress, and heating the device for about 10 minutes at 750° C. in a nitrogen environment. Thereafter, the layer of silicon nitride and the layer of silicon dioxide are removed by performing one or more etching processes. Then, raised source/drain regions are formed on the N-type devices by depositing epi semiconductor material in the source/drain areas of the device. Thereafter, source/drain implant regions are formed by performing an ion implantation process. A heating process is later performed to repair damage to the lattice structure of the substrate due to the amorphization implant process and the other ion implantation processes that were performed on the substrate up to this point in the process flow.
Prior art stress memorization techniques have a shortcoming of not forming stacking faults when the LOD (Length of Diffusion—the dimension between the edge of the gate structure at issue and the edge of the active region) is small. Thus, the stacking faults often do not form when they have to be located adjacent the free surface of the active region, i.e., the interface between the active region and the isolation material. FIG. 1A is a TEM photograph of an integrated circuit product 10 that includes a plurality of NMOS transistors formed above an active region 11 defined in a semiconductor substrate by an illustrative isolation region 16. As depicted, the transistors include a gate electrode structure 12 and raised source/drain regions 13. Ideally, by performing stress memorization techniques, stacking faults 14 (sometimes referred to as edge dislocations within the industry) will be formed in the active region 11 underneath the raised source/drain areas 13 of the devices. Ideally, for current generation devices with very small gate lengths and very tight gate spacing (pitch), the stacking faults 14 will have an inverted “V” shaped configuration, as depicted in the dashed-line region 15, for a [100] substrate. The stacking faults 14 may have a configuration other than the depicted inverted “V” for devices formed on substrates other than a [100] substrate, i.e., the angle of the downward-pointing “legs” of the inverted “V” shaped stacking faults 14 may be different when the substrate has a different crystallographic orientation. In some applications, the dislocations may not even intersect one another, i.e., the stacking faults may not intersect one another so as to form the “apex” of the inverted “V” shaped stacking faults. Thus, the above reference to the stacking faults 14 having an inverted “V” shaped configuration is only a shorthand reference. However, with respect to the transistors formed adjacent the edge of the isolation region 16 (i.e., when the LOD is small), such stacking faults 14 do not form in the source/drain regions of the device, as reflected by the absence of such stacking faults 14 in the dashed-line regions 17. The lack of the stacking faults 14 indicates that the particular transistor device did not receive any significant benefit from performing the process operations associated with the SMT module, i.e., the source/drain regions of such NMOS devices do not have the desired stacking faults 14. Accordingly, the transistors where the stacking faults 14 are absent, or at least not fully formed, will not perform as well as a transistor device where the stacking faults 14 are present, as depicted in the dashed line region 15 shown in FIG. 1A. This can also lead to across wafer device performance variability. Some attempts have been made to use hydrogen-rich silicon nitride as the stress-inducing material layers and/or fluorine implant for SMT amorphization to improve the formation of the desired stacking faults 14. High junction leakage is another issue that is prevalent with typical prior art SMT processes.
The present disclosure is directed to various stress memorization techniques that reduce or eliminate one or more of the problems identified above. FIG. 1B depicts TEM photograph of an improved device prepared in accordance with the processes disclosed herein. As could be seen in FIG. 1B, the integrated circuit product 10 has fully formed stacking faults 14. The disclosed stress memorization techniques result in significant reductions in junction leakage and in across-wafer drive current variability as compared to prior art devices.